A So-called “band-gap” voltage reference circuits are well known in the art, and are used to provide an output voltage, often of around 1.2V, that is invariant with changes of temperature and also with changes in supply voltage. These circuits operate by providing an output that has one term that has a positive temperature coefficient and one term that has a negative temperature coefficient. These are added together by the circuit in appropriate proportions so that the overall temperature coefficient of the output is zero.
Bandgap circuits suitable for inclusion in an integrated circuit have long been known. The need for integrated circuits to operate off 1V (or lower) power supplies has also long been recognized.
Banba et al, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation”, Proc. IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, pp. 670-674, May 1999, discloses a bandgap voltage reference circuit that is designed for CMOS construction and to operate using a supply voltage of under 1V.
FIG. 1 is a schematic diagram of the bandgap circuit proposed by Banba et al. The circuit comprises an op-amp 1 whose output 2 is connected to the gates of PMOS transistors 3 and 4, which have their sources connected to a positive supply 5 (VDD); so transistors 3 and 4 provide equal currents I3 and I4 from their drains respectively. The drain of transistor 3 is connected to a ground power supply 6 (VSS) via both a resistor 7 and a forward biased diode 8 arranged in parallel. The drain of transistor 4 is connected to VSS via a resistor 9. Connected in parallel with the resistor 9 is a network comprising a resistor 10 connected in series with a set of N forward biased diodes 11 connected in parallel with each other.
The drains of transistors 3 and 4 are also connected respectively to the inverting and non-inverting inputs of op-amp 1. Op-amp 1 operates to ensure that the voltages (VINN and VINP) at its inverting and non-inverting inputs are equal (since the op-amp has very high gain). Resistors 7 and 9 have the same resistance, with the result that the currents through them I7 and I9 respectively are equal (since VINN and VINP are equal), which in turn means that the current through diode 8 (I8) and that, I10, through the network comprising resistor 10 and diodes 11 are equal (remember also that I3 and I4 are equal).
Now, the output 2 of the op-amp 1 is also connected to the gate of a PMOS transistor 12; this has its source connected to VDD and its drain connected to ground via a resistor 13. The reference voltage VREF output of the circuit is that across the resistor 13 and may be calculated as follows:VREF=R13·I12 
where R13 is the resistance of resistor 13 and I12 is the current supplied from the drain of transistor 12.
Now, since I12=I4 because transistor 12 is the same size as transistors 3 and 4, and I4=I9+I10,VREF=R13·(I9+I10)=R13·(VINP/R9+V10/R10)                where V10 is the voltage across reistor 10, and furtherVREF=R13·(VINN/R9+V10/R10) since VINP=VINN.        
Now VINN is the forward bias voltage Vf8 across diode 8 and V10 is related to the forward bias voltage Vf11 across the N diodes 11 in a parallel (each carrying 1/N of the current flowing through diode 9) by:V10=VINP−Vf11=VINN −Vf11=Vf8−Vf11 but since (as is known in the art) for both diodes 8 and 11 Vf=VT. In (I/IS) where VT and IS are constants and are the same for all the diodes because diodes 8 and 11 are all identical, it follows that:
                              V          10                =                              V            T                    (                                    ln              ⁡                              (                                                      I                    8                                    ⁢                                      /                                    ⁢                                      I                    S                                                  )                                      -                          ln              ⁡                              (                                                      (                                                                  I                        8                                            ⁢                                              /                                            ⁢                      N                                        )                                    ⁢                                      /                                    ⁢                                      I                    S                                                  )                                                                                      =                                    V              T                        ·                          ln              ⁡                              (                N                )                                                    ,            and that thereforeVREF=R13·(Vf8/R9+VT·In(N)/R10). (This analysis is disclosed by Banba et al.).
Thus the reference voltage VREF depends on the forward bias voltage developed by a diode, which decreases with temperature, and on the constant VT (the “thermal voltage”) which increases with temperature. These two effects can be balanced by the choice of resistor values. The reference voltage VREF is fairly independent of the temperature effects on the resistances since it depends on ratios of resistance values.
The circuit is also provided with a transistor 14 which is turned on by a RESET signal during a power-up or reset operation. Transistor 14 is then turned off and the circuit is allowed to find its operating point. Switching on this transistor apparently establishes currents I4, I3 and I12 at the maximum possible values. It is believed however that once transistor 14 is turned off (by the RESET signal) the bandgap reference circuit will not reliably establish itself at the desired stable operating point, of which there are at least two. Since the circuit is released abruptly it may pass straight through the desired operating point to the stable state where the inputs to the op-amp are OV and no currents flow.
Waltari and Halonen, “Reference Voltage Driver for Low-Voltage CMOS A/D Converters”, Proc. IEEE International Conference on Electronics, Circuits and Systems, pp. 28-31, December 2000 (available at least at http://www.ecdl.hut.fi/˜mwa/publications), discloses a similar bandgap voltage reference circuit that is also designed to operate using a supply voltage of under 1V; in fact, as they say, they took the bandgap circuit of Banba et al and made some modifications.
FIG. 2 shows the circuit proposed by Waltari and Halonen. This uses similar reference numerals for parts similar to those of the circuit of FIG. 1. In this circuit only a proportion of the voltages (i) across the diode 8, or (ii) the network of diodes 11 and the resistor 10, are fed back to their op amp 1, which is said to be to move those voltages into a suitable range for input to their op amp 1. This is done by splitting each of the resistors 7 and 9 into two (7a and 7b; 9a and 9b) and taking the op-amp inputs from the nodes in between the respective resistor pairs.
Another modification is cascode transistors 21, 22 and 23 which have their current paths connected respectively in series between the drains of transistors 3, 4 and 12 and resistor 7, resistor 9 and resistor 13 respectively. The gates of the transistors are connected to a bias VbiasC provided by a bias circuit 24, which is responsive to the output of the op-amp. The cascode transistors are employed to improve the output impedance of the current sources formed by transistors 3, 4 and 12.
Waltari and Halonen also provide a start-up circuit. This is shown in FIG. 3. The start-up circuit 30 comprises an NMOS transistor 31 controlled by the voltage across diode 8 (via connection 32 to the circuit of FIG. 2). When that voltage falls below the threshold voltage of that transistor 31, the transistor 31 is off and so current is drawn through a resistor 33 via transistor 34. This current is mirrored via transistors 34, 35 and 36 and 37 and is injected back into the node monitored by transistor 31, which node is supplied with current by transistor 3, in order to ensure that current is supplied to diode 8 and resistor 7, thereby avoiding the alternative and undesirable operating point in which the voltage across the diode 8 and the resistor 9 is zero. When the reference circuit is in its desired operating point transistor 31 is on and draws all the current from resistor 33 leaving no (i.e. zero) current to be mirrored by transistor 34 to transistor 37. The startup circuit 30 also injects a current into the bias circuit, in that situation (from transistor 38 via connection 32).
Waltari and Halonen say that, when the voltage across the diode 8 is well above the threshold of transistor 31, the startup circuit has no effect on their bangap circuit.
Both Banba et al and Waltari and Halonen use diode connected PNP bipolar transistors for their diodes, which can be fabricated as vertical devices in the CMOS process.